Techniques for memory cell degradation protection

A memory system, comprising:

• one or more memory devices;
• and
• processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
• monitor a temperature associated with the memory system;
• adjust a counter by a first value based at least in part on the temperature satisfying a first threshold;
• and
• perform one or more protection operations on one or more blocks of memory cells of the memory system based at least in part on the counter satisfying a second threshold, the one or more protection operations comprising programming a respective data pattern to each of the one or more blocks of memory cells.

A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:

• monitor a temperature associated with a memory system;
• adjust a counter by a first value based at least in part on the temperature satisfying a first threshold;
• and
• perform one or more protection operations on one or more blocks of memory cells of the memory system based at least in part on the counter satisfying a second threshold, the one or more protection operations comprising programming a respective data pattern to each of the one or more blocks of memory cells.