Semiconductor device, method for designing the same, and method for manufacturing the same
AssigneeKioxia Corporation
InventorsYoshinori WATANABE, Satoshi YAMANO
Life of this patent
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Abstract
According to an embodiment, a semiconductor device includes a first cell. The first cell includes, a first PMOS transistor, a second PMOS transistor arranged side by side with the first PMOS transistor, a first NMOS transistor, a second NMOS transistor arranged side by side with the first NMOS transistor, and a seventh interconnect not electrically coupled to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.
Claims20
A semiconductor device comprising a first cell, the first cell including:
- a first PMOS transistor;
- a second PMOS transistor arranged side by side with the first PMOS transistor in a first direction and configured to share one end with one end of the first PMOS transistor;
- a first NMOS transistor arranged side by side with the first PMOS transistor in a second direction intersecting the first direction;
- a second NMOS transistor arranged side by side with the first NMOS transistor in the first direction and configured to share one end with one end of the first NMOS transistor;
- a first interconnect electrically coupled to another end of the first PMOS transistor;
- a second interconnect electrically coupled to the one end of the first PMOS transistor and the one end of the second PMOS transistor;
- a third interconnect electrically coupled to another end of the second PMOS transistor;
- a power supply voltage interconnect extending in the first direction, provided above the first interconnect, the second interconnect, and the third interconnect, and electrically coupled to the first interconnect, the second interconnect, and the third a fourth interconnect electrically coupled to another end of the first NMOS transistor;
- a fifth interconnect electrically coupled to the one end of the first NMOS transistor and the one end of the second NMOS transistor;
- a sixth interconnect electrically coupled to another end of the second NMOS transistor;
- a ground voltage interconnect extending in the first direction, provided above the fourth interconnect, the fifth interconnect, and the sixth interconnect, and electrically coupled to the fourth interconnect, the fifth interconnect, and the sixth interconnect;
- and
- a seventh interconnect provided in the same layer as the first to sixth interconnects and not electrically coupled to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.
A method for designing a semiconductor device, the method comprising:
- placing a plurality of first cells;
- interconnect-coupling the first cells;
- placing a plurality of second cells in a region where the first cells are not placed;
- changing at least one of the second cells to a logic cell and changing at least another one of the second cells to a third cell;
- and
- coupling the logic cell to a first interconnect passing through the third cell and not electrically coupled to the third cell.
A method for manufacturing a semiconductor device, the method comprising:
- placing a plurality of first cells;
- interconnect-coupling the first cells;
- placing a plurality of second cells in a region where the first cells are not placed;
- making a mask for use in formation of a transistor;
- manufacturing a transistor based on the mask;
- changing at least one of the second cells to a logic cell and changing at least another one of the second cells to a third cell;
- and
- coupling the logic cell to a first interconnect passing through the third cell and not electrically coupled to the third cell,
- wherein the making the mask and the coupling the logic cell and the first interconnect are executed in parallel.
Dependencies are inferred from the claim text.