Consolidation of staircase area etch and cmos contact area etch in 3d nand

Abstract

Systems, apparatuses, and methods may provide for technology that simultaneously forms staircase areas and CMOS (complementary metal-oxide-semiconductor) contact areas in three-dimensional (3D) NAND memory. A 3D NAND memory includes a first CMOS contact area and a first staircase area. The first CMOS contact area is formed through a plurality of sequential chops. The first staircase area is formed through a plurality of sequential staircase chops. The first CMOS contact area is formed through the plurality of sequential chops being performed simultaneous to the plurality of sequential staircase chops.

Dependencies are inferred from the claim text.