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US 2025/0219964 A1Published application
System-in-package network processors
AssigneeAltera Corporation
InventorsKevin Clark, Scott J. Weber, Ravi Prakash Gutala, Aravind Raghavendra Dasu
Life of this patent
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Abstract
This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.
Claims20
An integrated circuit device comprising:
- a base die that comprises memory;
- and
- a processor die coupled to the base die via an interface, wherein the processor die and the base die are vertically aligned so that the base die is vertically below at least a portion of a surface area of the processor die with a region of the processor die being vertically aligned with a corresponding region-aligned memory of the memory of the base die that is allocated to the region, wherein the processor die is to implement a processing function that uses the region-aligned memory.
A system comprising:
- a memory;
- and
- a processing device comprising:
- a base die that comprises on-package memory comprising a plurality of regions;
- and
- a processor die having a plurality of regions, wherein the processor die and the base die are vertically aligned so the base die is vertically below at least a portion of a surface area of the processor die with the plurality of regions of the base die vertically aligned to corresponding regions of the plurality of regions of the processor die, and the processor die is to implement a processing function that uses region-aligned memory.
3 more elements
A system comprising:
- a memory die that comprises on-package memory comprising a plurality of regions;
- and
- a network processor die to implement a network processor and having a plurality of regions, wherein the network processor die and the memory die are vertically aligned so the memory die is vertically below at least a portion of a surface area of the network processor die with the plurality of regions of the memory die vertically aligned to corresponding regions of the plurality of regions of the network processor die, and the network processor die is operable to implement a processing function that uses region-aligned memory.
Dependencies are inferred from the claim text.