Storage device having latching units serially connected for in-memory arithmetic operations

A method of comprising:

• setting each latching unit in an array of latching units to a forward-connection mode for a duration of a first time period while each inter-unit transmission switch in a plurality of inter-unit transmission switches is at a connected state, wherein each latching unit having a first bit node and a second bit node, wherein each pair of two adjacent latching units is coupled together through an inter-unit transmission switch which connects the second bit node in a first one of the two adjacent latching units with the first bit node in a second one of the two adjacent latching units;
• after the first time period, setting each latching unit in the array of latching units to a latch mode and setting each inter-unit transmission switch to a disconnected state;
• setting each latching unit in the array of latching units to a backward-connection mode for a duration of a second time period while each inter-unit transmission switch is at a connected state;
• and
• after the second time period, setting each latching unit in the array of latching units to a latch mode and setting each inter-unit transmission switch to a disconnected state.

A storage device comprising:

• an array of at least four latching units, wherein each latching unit comprises:
• a first inverter and a first transmission switch serially connected between a first bit node and a second bit node, the first inverter having an input configured to receive a voltage from the first bit node either directly or through the first transmission switch, and
• a second inverter and a second transmission switch serially connected between the second bit node and the first bit node, the second inverter having an input configured to receive a voltage from the second bit node either directly or through the second transmission switch;
• and
• a plurality of at least three inter-unit transmission switches, wherein each inter-unit transmission switch joining two adjacent latching units is configured to couple the second bit node of a first one of the two adjacent latching units with the first bit node of a second one of the two adjacent latching units.