Electronic device
AssigneeRenesas Electronics Corporation
InventorsRyuichi OIKAWA, Shuuichi KARIYAZAKI
Life of this patent
Estimating the term…
Abstract
A plurality of wirings included in a wiring substrate includes: a plurality of first wirings for propagating a first clock signal and a first chip select signal to first and second memory devices mounted on a front surface; and a plurality of second wirings for propagating a second clock signal and a second chip select signal to third and fourth memory devices mounted on a back surface. The plurality of first wirings is provided in a wiring layer, which is closer to the front surface, of a plurality of wiring layers, and the plurality of second wirings is provided in a wiring layer, which is closer to the back surface, of the wiring layers.
Claims15
An electronic device comprising:
- a wiring substrate having a first surface, a second surface opposite the first surface, a plurality of wiring layers and a plurality of wirings;
- a first memory device mounted on the first surface;
- a second memory device mounted on the first surface;
- a third memory device mounted on the second surface;
- a fourth memory device mounted on the second surface;
- and
- a control device mounted on the first surface, the control device being configured to access each of the first memory device and the second memory device by using a common first clock signal and a common first chip select signal, and the control device being configured to access each of the third memory device and the fourth memory device by using a common second clock signal and a common second chip select signal,
- wherein the plurality of wirings includes:
- a plurality of first wirings through which the common first clock signal and the common first chip select signal are propagated;
- and
- a plurality of second wirings through which the common second clock signal and the common second chip select signal are propagated,
- wherein the plurality of first wirings is provided in a wiring layer, which is closer to the first surface than the second surface, of the plurality of wiring layers, and
- wherein the plurality of second wirings is provided in a wiring layer, which is closer to the second surface than the first surface, of the plurality of wiring layers.
An electronic device comprising:
- a wiring substrate having a first surface, a second surface opposite the first surface, a plurality of wiring layers and a plurality of wirings;
- a first memory device mounted on the first surface;
- a second memory device mounted on the first surface;
- and
- a control device mounted on the first surface or the second surface, the control device being configured to access each of the first memory device and the second memory device by using a common clock signal and a common chip select signal,
- wherein when it is assumed that each of a cycle of the common first clock signal and a cycle of the common second clock signal is “Tck” and that a distance between the first memory device and the second memory device is “Lm”, “Lm” is defined based on a propagation delay time of “Tck/2”.
Dependencies are inferred from the claim text.