Self-aligned back-side gate vias
AssigneeIntel Corporation
InventorsEhren Mannebach, Shaun Mills, Joseph D’Silva, Mauro Kobrinsky
Life of this patent
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AssigneeIntel Corporation
InventorsEhren Mannebach, Shaun Mills, Joseph D’Silva, Mauro Kobrinsky
Estimating the term…
Transistor structures between and coupled to front- and back-side interconnect layers may have precisely aligned arrays of contacts and dielectric structures over and under the transistor structures. Back-side dielectric plugs may electrically isolate source and drain regions contacted on the front side from back-side interconnect lines. Back-side dielectric plugs may have a seam indicating plug formation from the back side, and the seam may be on a side contacting a back-side interconnect line. Spacer layers may insulate back-side gate contacts from adjacent back-side contacts. Contacts and dielectric structures on a back side may be formed using directed self-assembly of sacrificial materials aligned to sacrificial structures on source and drain regions and revealed on a substrate back side.
An apparatus, comprising:
An apparatus, comprising:
A method, comprising:
Dependencies are inferred from the claim text.