Display panel

A display panel, comprising:

• a plurality of pixel columns including a plurality of odd-numbered pixel columns and a plurality of even-numbered pixel columns arranged alternately in sequence in a row direction, wherein each of the pixel columns comprises three adjacent sub-pixel columns;
• a plurality of data lines, each of the data lines being connected to a sub-pixel row of the display panel;
• a data driver connected to the data lines and disposed in an arrangement direction of the pixel columns;
• a plurality of scan lines, each of the scan lines being connected to one of the sub-pixel columns;
• and
• a gate drive circuit disposed in an extension direction of the pixel columns and connected to the plurality of scan lines, the gate drive circuit comprising:
• a first gate drive group connected to a first odd-numbered pixel column of the odd-numbered pixel columns through 3 scan lines of the scan lines;
• a second gate drive group connected to a first even-numbered pixel column in the row direction of the even-numbered pixel columns through 3 scan lines of the scan lines;
• at least one third gate drive group, each of the third gate drive groups being connected to an other odd-numbered pixel column in the row direction of the odd-numbered pixel columns through 3 scan lines of the scan lines;
• and
• at least one fourth gate drive group, each of the fourth gate drive groups being connected to an other even-numbered pixel column of the even-numbered pixel column s through 3 scan lines of the scan lines,
• wherein the first gate drive group, the second gate drive group, the third gate drive group, and the fourth gate drive group are cascaded to scan a different sub-pixel column each time in a first mode, and
• the first gate drive group and the third gate drive group are cascaded, the second gate drive group and the fourth gate drive group are cascaded, the first gate drive group and the second gate drive group are configured to respectively synchronously scan the first odd-numbered pixel column and the first even-numbered pixel column, and the third gate drive group and the fourth gate drive group are configured to respectively synchronously scan the second odd-numbered pixel column and the second even-numbered pixel column in a second mode;
• wherein an input terminal of the gate drive circuit is connected to a mode control signal terminal, the mode control signal terminal is configured to output a mode control signal,
• wherein the gate drive circuit further comprises a shift register, the shift register comprises a first-type shift register, a second-type shift register, a third-type shift register, and a fourth-type shift register;
• wherein the first-type shift register is configured to output a first-stage gate drive signal based on a start signal and a first clock signal;
• the second-type shift register is configured to output a y-th-stage gate drive signal based on a (y−1)-th-stage gate drive signal and one of a second clock signal, a third clock signal, a fifth clock signal, and a sixth clock signal, wherein y is 2, 3, 5, 6, 8, 9, 11, 12, and so on;
• the third-type shift register is configured to output a fourth-stage gate drive signal based on the mode control signal, a fourth clock signal, the first-stage gate drive signal, and the start signal;
• the fourth-type shift register is configured to output a k-th-stage gate drive signal based on the mode control signal, a (k−1)-th-stage gate drive signal, and a (k−4)-th-stage gate drive signal, and one of a first clock signal or a fourth clock signal, where k is 7, 10, 13, 16, 19, and so on;
• in the first mode, the first clock signal and the sixth clock signal have a same waveform and phases sequentially delayed;
• and
• in the second mode, the first clock signal and the fourth clock signal have a same waveform and a same phase, the second clock signal and the fifth clock signal have a same waveform and a same phase, and the third clock signal and the sixth clock signal have a same waveform and a same phase.