US 2025/0211341 A1 · TRANSCEIVER LOOPBACK TESTING

Abstract

A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

Claims20

Dependent claims

A transceiver circuit, comprising:

a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data;
a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, wherein the serializer circuit comprises a serializer data storage device, and wherein the serializer data storage device lacks circuit structures for scanability;
a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, wherein the deserializer circuit comprises a deserializer data storage device, and wherein the deserializer data storage device lacks circuit structures for scanability;
and
a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

2 more elements

A system, comprising:

a controller;
and
a transceiver circuit, comprising:
a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data;
a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, wherein the serializer circuit comprises a serializer data storage device, and wherein the serializer data storage device lacks circuit structures for scanability;
a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, wherein the deserializer circuit comprises a deserializer data storage device, and wherein the deserializer data storage device lacks circuit structures for scanability;
and
a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data,
wherein the controller is configured to provide the serial stimulus data to the first register circuit with a first scan operation, and wherein the controller is configured to receive the serial response data from the second register circuit in a second scan operation.

6 more elements

A method of testing a transceiver circuit, the method comprising:

with a controller, asserting a first scan enable signal, the first scan enable signal causing first and second resettable clock circuits of the transceiver circuit to be reset to a predetermined state;
with the controller, providing serial stimulus data to a first register circuit of the transceiver circuit while the first scan enable signal is asserted;
with the controller, causing the transceiver circuit to operate in a loopback mode to generate serial response data;
with the controller, asserting a second scan enable signal, the second scan enable signal causing the first and second resettable clock circuits of the transceiver circuit to be reset to a predetermined state;
with the controller, receiving the serial response data from a second register circuit while the second scan enable signal is asserted;
and
with the controller, processing the serial response data to test functionality of the transceiver circuit.

4 more elements

Dependencies are inferred from the claim text.

Transceiver loopback testing

Life of this patent

Transceiver loopback testing

Life of this patent

Abstract

Claims20