A Two-Dimensional Discrete Fourier Transform Hardware Accelerator

A method for performing two-dimensional discrete Fourier transformation using a hardware accelerator that comprises of an ultrasonic transmitter, an ultrasonic receiver and a lens provided between the ultrasonic transmitter and the ultrasonic receiver, the method comprising:

• receiving, using the ultrasonic transmitter, input and control signals;
• receiving and storing, using the ultrasonic transmitter, input signals from the input data interface block and selectively providing, based on the control signals, the input signals to an array of transmitter pixels, whereby each transmitter pixel comprises a I path modulation block that is provided with a first set of quadrature phase carrier signals, and a Q path modulation block that is provided with a second set of quadrature phase carrier signals;
• transmitting to the lens, using the array of transmitter pixels, ultrasonic waves generated by the I and Q path modulation blocks based on the input signals and the first and second sets of quadrature phase carrier signals;
• down-converting, using an array of receiver pixels provided within the ultrasonic receiver, ultrasonic waves received from the lens to I and Q baseband signals based on third and fourth sets of quadrature phase carrier signals, whereby each receiver pixel comprises an IQ demodulator that is provided with the third and the fourth set of quadrature phase carrier signals;
• converting, using the ultrasonic receiver, the I and Q baseband signals received from the receiver pixels to digital representations.

A two-dimensional discrete Fourier transform sub-system comprising:

• a transmitter block comprising:
• an input data interface block configured to receive input and control signals;
• a memory module configured to receive and store input signals from the input data interface block and based on the control signals, to selectively provide the input signals to an array of transmitter pixels,
• whereby each transmitter pixel comprises a I path modulation block that is provided with a first set of quadrature phase carrier signals, and a Q path modulation block that is provided with a second set of quadrature phase carrier signals, and
• whereby the array of transmitter pixels is configured to transmit to a lens provided between the transmitter block and a receiver block, ultrasonic waves generated by the I and Q path modulation blocks based on the input signals and the first and second sets of quadrature phase carrier signals;
• the receiver block comprising:
• an array of receiver pixels, whereby each receiver pixel comprises an IQ demodulator that is provided with a third and a fourth set of quadrature phase carrier signals, and whereby each receiver pixel is configured to use the IQ demodulator in each receiver pixel to down convert ultrasonic waves received from the lens to I and Q baseband signals based on the third and fourth sets of quadrature phase carrier signals;
• a plurality of analog baseband and analog-to-digital converter (ADC) pairs configured to convert the I and Q baseband signals received from the receiver pixels to digital representations.