Dfe-based peaking techniques for high-speed transmitters

Abstract

A circuit for driving digital-to-analog converter (DAC) comprising a serializer configured to combine multiple signals to one input signal to drive a forward inverter coupled to a first node with a first impedance in serial configuration and a first capacitance in shunt configuration. The circuit includes a chain of inverters coupled in series to transfer the input signal from the first node to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter between the third node and the first node to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node. A second feedback inverter can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

Dependencies are inferred from the claim text.