Semiconductor package

A semiconductor package, comprising:

• a lower substrate comprising a first region and a second region spaced apart from the first region in a first direction;
• a first semiconductor chip on the first region, the first semiconductor chip is electrically connected to the lower interconnection layer;
• connection structures on the first region and the second region, the connection structures surrounding the first semiconductor chip;
• support members disposed on at least a portion of connection structures adjacent to side surfaces of the first semiconductor chip and edges of the lower substrate of the connection structures;
• an upper substrate disposed on the first semiconductor chip and the connection structures and overlapping therewith in a vertical direction, the upper substrate comprising an upper interconnection layer;
• a second semiconductor chip on the upper substrate, the second semiconductor chip is electrically connected to the upper interconnection layer and overlaps the second region in the vertical direction;
• and
• a third semiconductor chip on the upper substrate, the third semiconductor chip is spaced apart from the second semiconductor chip in a horizontal direction and overlaps the first semiconductor chip in the vertical direction.

A semiconductor package, comprising:

• a lower substrate comprising a first region and a second region spaced apart from the first region in a first direction;
• a capacitor embedded in the lower substrate;
• a first semiconductor chip on the first region, the first semiconductor chip is electrically connected to the lower interconnection layer;
• first connection structures on the first region, the first connection structures are adjacent to side surfaces of the first semiconductor chip;
• second connection structures on the second region, the second connection structures are disposed at a same level as the first connection structures;
• support members disposed on at least a portion of the first connection structures and a portion of the second connection structures;
• an upper substrate disposed on the first semiconductor chip, the first connection structures and the second connection structures and overlapping the lower substrate in a vertical direction, the upper substrate comprising an upper interconnection layer;
• a second semiconductor chip on the upper substrate, the second semiconductor chip is electrically connected to the upper interconnection layer and overlaps the second region in the vertical direction;
• and
• a third semiconductor chip on the upper substrate, the third semiconductor chips is spaced apart from the second semiconductor chip in a horizontal direction and overlaps the first semiconductor chip in the vertical direction.