Semiconductor package and manufacturing method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorJeongki JANG
Life of this patent
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Abstract
A semiconductor package includes: a semiconductor chip and an electronic component mounted on a substrate; and a molding layer disposed on the substrate and covering the semiconductor chip and the electronic component, wherein the electron component includes a plurality of grooves, wherein the plurality of grooves are disposed on a surface of the electronic component, wherein the plurality of grooves have a first width at an entrance portion of the plurality of grooves and a second width greater than the first width below the entrance portion, and wherein the molding layer is disposed in the plurality of grooves.
Claims20
A semiconductor package comprising:
- a semiconductor chip and an electronic component mounted on a substrate;
- and
- a molding layer disposed on the substrate and covering the semiconductor chip and the electronic component,
- wherein the electron component comprises a plurality of grooves, wherein the plurality of grooves are disposed on a surface of the electronic component,
- wherein the plurality of grooves have a first width at an entrance portion of the plurality of grooves and a second width greater than the first width below the entrance portion, and
- wherein the molding layer is disposed in the plurality of grooves.
A semiconductor package manufacturing method comprising:
- forming an electronic component;
- forming a plurality of grooves on a surface of the electronic component;
- mounting a semiconductor chip and the electronic component on the substrate;
- and
- forming, on the substrate, a molding layer covering the semiconductor chip and the electronic component, wherein
- the plurality of grooves have a first width at an entrance portion of the grooves and a second width greater than the first width, and
- the molding layer is formed in the plurality of grooves.
Dependencies are inferred from the claim text.