Memory bitcell with balanced diffusion layout
AssigneeIntel Corporation
InventorsAmlan Ghosh, Feroze Merchant
Life of this patent
Estimating the term…
Abstract
Various embodiments provide apparatuses, systems, and methods for a memory bitcells with a balanced distribution of (e.g., equal numbers of) p-type transistors (e.g., p-type metal-oxide-semiconductor (PMOS)) and n-type transistors (e.g., n-type metal-oxide-semiconductor (NMOS)). For example, the memory bitcell may include an NMOS passgate transistor and a PMOS passgate transistor coupled to the bit node. The memory bitcell may further include another NMOS passgate transistor and another PMOS passgate transistor coupled to the bit bar node. Other embodiments may be described and claimed.
Claims20
A memory circuit comprising:
- a bit node to store a logic value of a bit;
- a first passgate transistor with a source or drain terminal coupled to the bit node, wherein the first passgate transistor is a p-type metal-oxide-semiconductor (PMOS) transistor;
- and
- a second passgate transistor with a source or drain terminal coupled to the bit node, wherein the second passgate transistor is an n-type metal-oxide-semiconductor (NMOS) transistor, and wherein both the first and second passgate transistors are turned on for a write operation to write the logic value to the bit node.
A dual-ported memory circuit comprising:
- a bit node to store a logic value of a bit;
- a first passgate transistor with a first source or drain terminal coupled to the bit node, a second source or drain terminal coupled to a first bitline associated with a first port, and a gate terminal coupled to a first word line, wherein the first passgate transistor is a p-type metal-oxide-semiconductor (PMOS) transistor;
- and
- a second passgate transistor with a first source or drain terminal coupled to the bit node, a second source or drain terminal coupled to a second bitline associated with a second port, and a gate terminal coupled to a second word line, wherein the second passgate transistor is a n-type metal-oxide-semiconductor (NMOS) transistor.
A system comprising:
- processor circuitry that includes one or more processor cores;
- and
- memory circuitry coupled to the processor circuitry, wherein the memory circuitry includes an array of bitcells, and wherein an individual bitcell of the array includes:
- a bit node to store a logic value of a bit;
- a first passgate transistor with a first source or drain terminal coupled to the bit node, a second source or drain terminal coupled to a write bit line, and a gate terminal coupled to a write word line;
- and
- a second passgate transistor with a first source or drain terminal coupled to the bit node, a second source or drain terminal coupled to a read and write bit line, and a gate terminal coupled to a read and write word line.
Dependencies are inferred from the claim text.