Scalable centralized error queues in a processing architecture
AssigneeIntel Corporation
InventorsDavid Puffer, Soumya S. Sonnenahalli, Vaidyanathan Krishnamoorthy
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AssigneeIntel Corporation
InventorsDavid Puffer, Soumya S. Sonnenahalli, Vaidyanathan Krishnamoorthy
Estimating the term…
An apparatus to facilitate scalable centralized error queues in a processing architecture is disclosed. The apparatus includes a processor comprising a systems interface hosting an error aggregator, wherein the processor is to host at least one centralized error queue in the error aggregator, the at least one centralized error queue is to store error logs for errors detected by components of the processor; receive an error reporting message from a component of the components of the processor, the error reporting message corresponding to an error detected by the component; and log the error as an entry in the at least one centralized error queue based on an error type of the error.
An apparatus comprising:
A method comprising:
A non-transitory computer-readable medium having instructions stored thereon, which when executed by one or more processors, cause the one or more processors to:
Dependencies are inferred from the claim text.