Device, method and system to provide prediction state information of a processor

Abstract

Techniques and mechanisms for automatically saving and recovering microarchitectural prediction state information of a processor core. In an embodiment, a core comprises prediction circuitry which generates microarchitectural prediction state information based on an execution of a software process by the core. A prediction state manager of the processor detects a context switch of the processor and, based on such detection, automatically saves a version of the microarchitectural prediction state information to a repository which is external to the core. The microarchitectural prediction state information is available to be recovered from the repository to facilitate a resumed execution of the software process. In another embodiment, the microarchitectural prediction state information is saved to, or recovered from, the repository independent of an instruction of the software process, if any, which specifies that such saving or recovery is to be performed.

Dependencies are inferred from the claim text.