System, apparatus and method for lockstep corrected error reporting, data poisoning and potential recovery mechanisms
AssigneeIntel Corporation
InventorsSamuel Mattord, Arvind Raman
Life of this patent
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Abstract
In one embodiment, an apparatus includes: first and second cores to execute instructions, and an interface circuit coupled to the first and second cores. In a lockstep mode in which the first and second cores are to execute redundantly, the interface circuit is to identify a miscompare between the first core and the second core that is due to a corrected error in one of the first core or the second core, and indicate the miscompare as a recoverable error. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- a first core to execute instructions;
- a second core to execute instructions, wherein in a lockstep mode, the first core and the second core are to execute in lockstep;
- and
- an interface circuit coupled to the first core and the second core, wherein in the lockstep mode the interface circuit is to identify a miscompare between the first core and the second core that is due to a corrected error in one of the first core or the second core, and indicate the miscompare as a recoverable error.
At least one machine-readable storage medium comprising instructions that, when executed, cause a machine to perform a method comprising:
- identifying, in processor circuitry of a processor, a mismatch between first data output from a first core and first redundant data output from a second core while the first core and the second core are operating in a lockstep mode;
- determining whether the processor is enabled for poisoned miscomparison reporting;
- and
- in response to identifying the mismatch and determining that the processor is enabled for the poisoned miscomparison reporting, associating a poison indicator with the first data and sending the first data and the poison indicator to a memory hierarchy.
A system comprising:
- a processor comprising:
- a first register having a first field to store one or more first bits to enable or disable a corrected error indication for a miscomparison in a lockstep mode due to a corrected error;
- a first core to execute instructions;
- a second core to execute instructions, wherein in the lockstep mode, the first core and the second core are to execute redundantly;
- and
- interface circuitry coupled to the first core and the second core, wherein the interface circuitry is to identify a miscomparison between the first core and the second core that is due to a corrected error in one of the first core or the second core, and indicate the miscomparison as a recoverable error when the one or more first bits enable the corrected error indication;
- and
- a dynamic random access memory coupled to the processor.
Dependencies are inferred from the claim text.