Audio interface physical layer
AssigneeTexas Instruments Incorporated
InventorsAtul Kumar AGRAWAL, Abhijit Patki, Shaik BASHA
Life of this patent
Estimating the term…
Abstract
An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.
Claims20
An integrated circuit (IC), comprising:
- an input buffer having a buffer output;
- a first delay circuit having a first delay circuit input and a first delay circuit output, the first delay circuit input coupled to the buffer output;
- a second delay circuit having a second delay circuit input and a second delay circuit output, the second delay circuit input coupled to the first delay circuit output;
- a first logic gate having a first logic gate input, a second logic gate input, and a first logic gate output, the first logic gate input coupled to the first delay circuit output, and the second logic gate input coupled to the second delay circuit output;
- a second logic gate having a third logic gate input, a fourth logic gate input, and a second logic gate output, the third logic gate input coupled to the first logic gate output;
- and
- a tristatable output buffer having a control input, the control input coupled to the second logic gate output.
An integrated circuit (IC), comprising:
- a tristatable output buffer having a control input;
- an input buffer having a buffer output;
- a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output, the delay circuit input coupled to the buffer output;
- a tristate circuit coupled to the first delay circuit output and to the second delay circuit output, and the tristate circuit having a tristate circuit output coupled to the control input;
- a first latch having a first latch input, a first enable input, and a first latch output;
- a logic gate having a first logic gate input, a second logic gate input, and a logic gate output, the first logic gate input coupled to the delay circuit input, and the second logic gate input coupled to the first latch output;
- and
- a second latch having a second enable input and a second latch output, the second enable input coupled to the logic gate output, and the second latch output coupled to the control input.
The IC of claim 14, wherein the logic gate is an exclusive-NOR gate.
An integrated circuit (IC), comprising:
- an input buffer having a clock input and a buffer output;
- a tristatable output buffer having a control input;
- a first delay circuit having an input coupled to the buffer output and having a first delay circuit output;
- a second delay circuit having a second delay circuit input and a second delay circuit output, the second delay circuit input coupled to the first delay circuit output;
- and
- a tristate circuit coupled to the first delay circuit output and to the second delay circuit output, and the tristate circuit having a tristate circuit output coupled to the control input.
Dependencies are inferred from the claim text.