Method of manufacturing semiconductor memory device

A method of manufacturing a semiconductor memory device, the method comprising:

• forming a plurality of word lines, a plurality of channel structures, and a plurality of bit lines on a substrate, wherein the plurality of word lines extend in a first horizontal direction, wherein the plurality of channel structures are adjacent to the plurality of word lines and arranged in rows in the first horizontal direction, each channel structure of the plurality of channel structures comprising a channel pattern extending in a vertical direction, and wherein the plurality of bit lines extend in a second horizontal direction, different from the first horizontal direction, and each of the plurality of bit lines is electrically connected to a first end of the channel pattern of a corresponding one of the plurality of channel structures;
• forming, on the plurality of channel structures, a plurality of silicide material layers, each silicide material layer of the plurality of silicide material layers comprising an alloy of a semiconductor material and a metal, the metal comprising a eutectic composition;
• performing a metal-induced crystallization to convert the plurality of silicide material layers into a plurality of induced silicide material layers having a circular planar shape;
• forming a plurality of sacrificial semiconductor layers between the plurality of induced silicide material layers and upper surfaces of the plurality of channel structures, and forming a mold layer surrounding the plurality of sacrificial semiconductor layers;
• forming a plurality of capacitor holes by removing the plurality of sacrificial semiconductor layers;
• forming a plurality of lower electrodes that fill the plurality of capacitor holes, wherein each of the plurality of lower electrodes is electrically connected to a second end of the channel pattern of a corresponding one of the plurality of channel structures;
• removing the mold layer;
• forming a capacitor dielectric layer that covers surfaces of the plurality of lower electrodes;
• and
• forming an upper electrode that covers the capacitor dielectric layer.

A method of manufacturing a semiconductor memory device, the method comprising:

• forming a plurality of word lines, a plurality of back gate lines, a plurality of channel patterns, and a plurality of bit lines on a substrate, wherein the plurality of word lines extend in a first horizontal direction, wherein the plurality of back gate lines extend in the first horizontal direction and spaced apart from the plurality of word lines in a second horizontal direction different from the first horizontal direction, wherein the plurality of channel patterns are arranged between one word line, among the plurality of word lines, and one back gate line adjacent to the one word line, among the plurality of back gate lines, the plurality of channel patterns extending in a vertical direction, and wherein the plurality of bit lines extend below the plurality of channel patterns in the second horizontal direction different from the first horizontal direction and are electrically connected to first ends of the plurality of channel patterns;
• forming a plurality of connection structures by implanting impurities into upper portions of the plurality of channel patterns;
• forming, on the plurality of connection structures, a plurality of silicide material layers, each silicide material layer of the plurality of silicide material layers comprising an alloy of a semiconductor material and a metal, the metal comprising a eutectic composition;
• forming a plurality of sacrificial semiconductor layers, a mold layer, and a plurality of support patterns on the plurality of connection structures;
• forming a plurality of capacitor holes by removing the plurality of sacrificial semiconductor layers;
• forming a plurality of lower electrodes that fill the plurality of capacitor holes and are electrically connected to second ends of the plurality of channel patterns;
• removing the mold layer;
• forming a capacitor dielectric layer that covers surfaces of the plurality of lower electrodes and surfaces of the plurality of support patterns;
• and
• forming an upper electrode that covers the capacitor dielectric layer,
• wherein each sacrificial semiconductor layer of the plurality of sacrificial semiconductor layers comprises a plurality of sub-sacrificial semiconductor layers having a cylindrical shape, and the mold layer comprises a plurality of sub-mold layers, and
• wherein the forming the plurality of sacrificial semiconductor layers, the mold layer, and the plurality of support patterns comprises:
• heating and converting the plurality of silicide material layers into a plurality of induced silicide material layers having a circular planar shape;
• a first operation of forming, between the plurality of induced silicide material layers and upper surfaces of the plurality of connection structures, one sub-sacrificial semiconductor layer, among the plurality of sub-sacrificial semiconductor layers, by injecting a semiconductor material precursor and performing a metal-induced crystallization;
• a second operation of forming one sub-mold layer, among the plurality of sub-mold layers, that surrounds a portion of a side surface of the one sub-sacrificial semiconductor layer;
• a third operation of forming one support pattern, among the plurality of support patterns, which covers a side surface of an upper portion of the one sub-sacrificial semiconductor layer;
• and
• repeating the first operation, the second operation, and the third operation at least three times.