Integrated circuit and method of forming the same

An integrated circuit comprising:

• a first active region extending in a first direction, and being on a first level of a substrate, the first active region corresponding to a first set of transistors of a first dopant type;
• a second active region extending in the first direction, being on the first level, and being separated from the first active region in a second direction different from the first direction, the second active region corresponding to a second set of transistors of a second dopant type different from the first dopant type;
• a first set of contacts extending in the second direction, being on a second level different from the first level, the first set of contacts overlapping the second active region, a first cell boundary and a second cell boundary of the integrated circuit that extends in the second direction;
• a set of gates extending in the second direction, being on a third level different from the first level, the set of gates overlapping the first active region and the second active region, and being between the first set of contacts;
• a first power rail extending in the first direction, configured to supply a first supply voltage, and being on a fourth level different from the first level, the second level and the third level, the first power rail overlapping at least the first set of contacts;
• and
• a first set of vias between the first set of contacts and the first power rail, the first set of vias electrically coupling the first set of contacts and the first power rail together;
• wherein at least one of the first active region or the second active region extends continuously through the first cell boundary and the second cell boundary, and
• the first set of transistors includes a first transistor configured as a dummy transistor.

A method of fabricating an integrated circuit, the method comprising:

• fabricating a set of active regions of a set of transistors in a front-side of a substrate, the set of active regions extending in a first direction;
• depositing a first conductive material over the set of active regions on a first level thereby forming a first set of contacts for the set of transistors, the first set of contacts overlapping a first cell boundary and a second cell boundary, the first set of contacts extending in a second direction different from the first direction;
• fabricating a set of gates over the set of active regions on a second level, the set of gates extending in the second direction, the set of gates overlapping the set of active regions, and not overlapping the first cell boundary and the second cell boundary;
• fabricating a first set of vias over the first set of gates;
• and
• depositing a second conductive material over the first set of gates on a third level thereby forming a first set of power rails, the third level being above the first level and the second level, the first set of power rails being electrically coupled to at least the first set of gates by the first set of vias.