Semiconductor device

A semiconductor device, comprising:

• a lower transistor;
• and
• an upper transistor located at a higher vertical level than the lower transistor, wherein the lower transistor comprises
• a lower source/drain region,
• a lower gate structure and a lower isolation insulating layer that are in contact with a side surface of the lower source/drain region, wherein lower gates and lower nanosheets are alternately stacked in the lower gate structure, and
• a lower source/drain contact that is in contact with the lower source/drain region, wherein the upper transistor comprises
• an upper source/drain region,
• an upper gate structure and an upper isolation insulating layer that are in contact with a side surface of the upper source/drain region, wherein upper gates and upper nanosheets are alternately stacked in the upper gate structure, and
• an upper source/drain contact that is in contact with the upper source/drain region, wherein a bottom surface of the lower isolation insulating layer is located at a same vertical level as a bottom surface of the lower gate structure.

A semiconductor device, comprising:

• a lower transistor;
• and
• an upper transistor located at a higher vertical level than the lower transistor,
• wherein the lower transistor comprises
• a lower source/drain region, and
• a lower gate, a lower nanosheet, and a lower isolation insulating layer that are in contact with a side surface of the lower source/drain region, and
• the upper transistor comprises
• an upper source/drain region,
• an upper gate, an upper nanosheet, and an upper isolation insulating layer that are in contact with a side surface of the upper source/drain region, and
• an upper horizontal insulating layer disposed on the upper gate and at an uppermost end and that extends in one horizontal direction, wherein
• the lower gate and the lower nanosheet are stacked,
• the upper gate and the upper nanosheet are stacked,
• each of the lower gate and the lower nanosheet is spaced apart from the lower isolation insulating layer in a horizontal direction,
• each of the upper gate and the upper nanosheet is spaced apart from the upper isolation insulating layer in the horizontal direction, and
• a bottom surface of the lower isolation insulating layer is located at a same vertical level as a bottom surface of the lower gate at a lowermost end.