Merged backside contact isolation
AssigneeInternational Business Machines Corporation
InventorsLijuan Zou, Tao Li, Ruilong Xie, Chih-Chao Yang
Life of this patent
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Abstract
A semiconductor device includes a dielectric isolation bar disposed in a region between an n-type active region and a p-type active region. The dielectric isolation bar has a first tapered portion disposed within a contact where the contact connects to the n-type active region or the p-type active region and a second tapered portion that cuts through portions of a buried power rail layer, wherein the dielectric isolation bar electrically isolates a lateral portion of the contact from surrounding structures and separates portions of the buried power rail layer.
Claims20
A semiconductor device, comprising:
- a dielectric isolation bar disposed in a region between an n-type active region and a p-type active region, the dielectric isolation bar having:
- a first tapered portion disposed within a contact where the contact connects to one of the n-type active region and the p-type active region;
- and
- a second tapered portion that cuts through portions of a buried power rail layer, wherein the dielectric isolation bar electrically isolates a lateral portion of the contact from surrounding structures and separates portions of the buried power rail layer.
A semiconductor device, comprising:
- an n-type active region disposed adjacent to a p-type active region;
- a merged contact having a first portion connecting the n-type active region to a first buried power rail and a second portion connecting the p-type active region to second buried power rail;
- and
- a dielectric isolation bar disposed through the merged contact to cut the merged contact into the first portion and the second portion, the dielectric isolation bar disposed between the first buried power rail and the second buried power rail to electrically isolate the first portion of the merged contact from the second portion of the merged contact and the first buried power rail from the second buried power rail.
A semiconductor device, comprising:
- a first dielectric isolation bar disposed within a single contact between an n-type active region and an adjacent a p-type active region;
- and
- a second dielectric isolation bar disposed through a merged contact between an n-type active region and an adjacent a p-type active region, the second dielectric isolation bar separating the merged contact to connect one portion of the merged contact to the n-type active region and another portion of the merged contact to the p-type active region;
- the first dielectric isolation bar and the second dielectric isolation bar pass through a power rail layer to define buried power rails.
Dependencies are inferred from the claim text.