Transistors with Recessed Silicon Cap and Method Forming Same

An integrated circuit device comprising:

• a bulk semiconductor substrate;
• dielectric isolation regions over the bulk semiconductor substrate;
• a semiconductor region over the dielectric isolation regions, wherein the semiconductor region is between, and higher than, opposing parts of the dielectric isolation regions;
• a gate stack on the semiconductor region, the gate stack comprising a gate dielectric and a gate electrode over the gate dielectric;
• a gate spacer aside of the gate stack;
• a silicon cap layer between, and contacting both of, the semiconductor region and the gate stack, wherein the silicon cap layer directly contacts both of a top surface and sidewalls of the semiconductor region;
• a dielectric layer between and contacting the gate spacer and the silicon cap layer;
• and
• a source/drain region contacting both of the semiconductor region and the silicon cap layer, wherein the silicon cap layer forms a vertical interface with the source/drain region, and a part of the vertical interface is directly underlying the gate spacer, and is laterally recessed more toward a center of the gate stack than an outer sidewall of the dielectric layer.

An integrated circuit device comprising:

• a bulk semiconductor substrate;
• dielectric isolation regions over the bulk semiconductor substrate;
• a semiconductor region over the bulk semiconductor substrate, wherein the semiconductor region is between, and higher than, opposing parts of the dielectric isolation regions;
• a gate stack over the semiconductor region, the gate stack comprising a gate dielectric;
• a gate spacer on a sidewall of the gate stack, wherein the gate spacer comprises an inner sidewall contacting the gate stack, and an outer sidewall opposing the inner sidewall;
• a dielectric layer underlying and contacting the gate spacer, wherein the dielectric layer comprises:
• a first inner sidewall vertically aligned to a second inner sidewall of the gate spacer;
• and
• a first outer sidewall vertically aligned to a second outer sidewall of the gate spacer;
• a silicon cap layer comprising a top portion between and contacting the semiconductor region and the gate stack, and sidewall portions contacting sidewalls of the semiconductor region, wherein a bottom surface of the top portion of the silicon cap layer contacts a top surface of the semiconductor region to form a horizontal interface, and the horizontal interface comprises an end laterally between the first inner sidewall and the first outer sidewall;
• and
• a source/drain region contacting the semiconductor region and silicon cap layer.