Extended backside contact for stacked field-effect transistor

A semiconductor device comprising:

• a first transistor comprising a first source/drain region disposed on a side of the first transistor;
• a second transistor stacked on the first transistor and comprising a second source/drain region disposed on a side of the second transistor, wherein the second source/drain region is stacked on the first source/drain region;
• and
• a source/drain contact disposed under the first source/drain region, wherein a dimension of the source/drain contact is larger than a dimension of the first source/drain region such that at least one sidewall of the source/drain contact is out of alignment with at least one sidewall of the first source/drain region;
• wherein the first transistor comprises a plurality of channel layers contacting a dielectric layer of a gate cut portion.

A semiconductor device comprising:

• a stacked structure comprising a plurality of gate structures alternately stacked with a plurality of channel layers;
• at least one source/drain region disposed on a side of the stacked structure;
• and
• a source/drain contact disposed under the at least one source/drain region, wherein a dimension of the source/drain contact is larger than a dimension of the at least one source/drain region such that at least one sidewall of the source/drain contact is out of alignment with at least one sidewall of the at least one source/drain region;
• wherein the plurality of channel layers contact a dielectric layer of a gate cut portion.