Electron hole spin qubit transistor, and methods for forming a electron hole spin qubit transistor

A method for forming an electron-hole spin qubit transistor comprising the steps of:

• forming a hard mask layer on a base layer;
• forming a first plurality of nano size cavities in the hard mask layer;
• exposing the base layer to semiconductor reactive species, thereby forming a plurality of first compute semiconductor islands in said first plurality of nano size cavities;
• forming a second plurality of nano size cavities in the hard mask layer;
• exposing the base layer to semiconductor reactive species, thereby forming a plurality of second compute semiconductor islands in said second plurality of nano size cavities;
• forming a third plurality of nano size cavities in the hard mask layer;
• exposing the base layer to semiconductor reactive species, thereby forming, in said third plurality of nano size cavities:
• a plurality of first readout semiconductor islands, each of said plurality of first readout semiconductor islands being arranged within a distance in the range of 3-10 nm from each of said plurality of first compute semiconductor islands, and
• a plurality of second readout semiconductor islands, each of said plurality of second readout semiconductor islands being arranged within a distance in the range of 3-10 nm from each of said plurality of second compute semiconductor islands;
• removing the hard mask layer by wet etching or plasma etching, and embedding the formed plurality of first compute semiconductor islands, the formed plurality of second compute semiconductor islands, and the plurality of first and second readout semiconductor islands in a supporting material laterally overgrown over the semiconductor islands;
• forming at least one source terminal being in electrical contact with the plurality of first computing semiconductor islands via the supporting material;
• forming at least one drain terminal being in electrical contact with the plurality of second computing semiconductor islands via the supporting material;
• forming a plurality of first gate terminals arranged over each of the plurality of first computing semiconductor islands, the plurality of first gate terminals being configured for microwave modulation of the spin state of each of the plurality of first computing semiconductor islands;
• forming a plurality of second gate terminals arranged over each of the plurality of first readout semiconductor islands, the plurality of second gate terminals being configured for readout of a state of each of the plurality of first readout semiconductor islands;
• forming a plurality of third gate terminals arranged over each of the plurality of second computing semiconductor islands, the plurality of third gate terminals being configured for microwave modulation of the spin state of each of the plurality of second computing semiconductor islands;
• forming a plurality of fourth gate terminals arranged over each of the second readout semiconductor islands, the plurality of fourth gate terminals being configured for readout of a state of each of the plurality of second readout semiconductor islands.

A method for forming an electron-hole spin qubit transistor comprising the steps of:

• providing a layer structure comprising a plurality of semiconductor layers stacked over each other, each of the plurality of semiconductor layers being a unique alloy;
• forming a first hard mask layer on top of the plurality of semiconductor layers;
• forming a first plurality of nano size cavities through first hard mask layer and extending to a first layer of said plurality of semiconductor layers at a first depth;
• exposing the layer structure to a first semiconductor reactive species, thereby forming a plurality of first compute semiconductor islands in said first plurality of nano size cavities;
• forming a second hard mask layer on top of the plurality of semiconductor layers;
• forming a second plurality of nano size cavities through the second hard mask layer and extending to a second layer of said plurality of semiconductor layers at a second depth;
• exposing the layer structure to a second semiconductor reactive species, thereby forming a plurality of second compute semiconductor islands in said second plurality of nano size cavities;
• forming a third hard mask layer on top of the plurality of semiconductor layers;
• forming a third plurality of nano size cavities through the third hard mask layer and extending to a third layer of said plurality of semiconductor layers at a third depth;
• exposing the layer structure to a third semiconductor reactive species, thereby forming a plurality of first and second readout semiconductor islands in said third plurality of nano size cavities;
• wherein the first, second, and third depths differs by at least one layer of said semiconductor layers;
• removing all hard mask layers by wet etching or plasma etching;
• embedding the formed plurality of first compute semiconductor islands, the formed plurality of second compute semiconductor islands, and the formed plurality of first and second readout semiconductor islands in a supporting material laterally overgrown over the semiconductor islands;
• forming at least one source terminal being in electrical contact with the plurality of first computing semiconductor islands via the supporting material;
• forming at least one drain terminal being in electrical contact with the plurality of second computing semiconductor islands via the supporting material;
• forming a plurality of first gate terminals arranged over each of the plurality of first computing semiconductor islands, the plurality of first gate terminals being configured for microwave modulation of the spin state of each of the plurality of first computing semiconductor islands;
• forming a plurality of second gate terminals arranged over each of the plurality of first readout semiconductor islands, the plurality of second gate terminals being configured for readout of a state of each of the plurality of first readout semiconductor islands;
• forming a plurality of third gate terminals arranged over each of the plurality of second computing semiconductor islands, the plurality of third gate terminals being configured for microwave modulation of the spin state of each of the plurality of second computing semiconductor islands;
• forming a plurality of fourth gate terminals arranged over each of the second readout semiconductor islands, the plurality of fourth gate terminals being configured for readout of a state of each of the plurality of second readout semiconductor islands.