Semiconductor device
AssigneeFuji Electric Co., Ltd.
InventorYasuyuki HOSHI
Life of this patent
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Abstract
A semiconductor device, including: a plurality of unit cells formed in a semiconductor element region, each unit cell being a trench-type metal oxide semiconductor field effect transistor (MOSFET), and including a first trench; a gate runner provided in a gate runner region, which surrounds the semiconductor element region in a plan view of the semiconductor device; a ring electrode provided in a ring region, which surrounds the gate runner region in the plan view; and a termination region surrounding the ring region in the plan view. The ring region includes a second trench. At least a portion of the ring electrode is provided in the second trench.
Claims17
A semiconductor device comprising:
- a plurality of unit cells formed in a semiconductor element region, each unit cell being a trench-type metal oxide semiconductor field effect transistor (MOSFET), and including a first trench;
- a gate runner provided in a gate runner region, which surrounds the semiconductor element region in a plan view of the semiconductor device;
- a ring electrode provided in a ring region, the ring region surrounding the gate runner region in the plan view;
- and
- a termination region surrounding the ring region in the plan view, wherein
- the ring region includes a second trench, and at least a portion of the ring electrode is provided in the second trench.
A semiconductor device comprising:
- a plurality of unit cells formed in a semiconductor element region, each unit cell being a trench-type metal oxide semiconductor field effect transistor (MOSFET), and including:
- a first trench,
- a source region that is of a first conductivity type and in contact with the first trench, and
- a base layer that is of a second conductivity type and in contact with the first trench, at least a portion of the base layer being provided under the source region;
- a gate runner provided in a gate runner region, which surrounds the semiconductor element region in a plan view of the semiconductor device;
- a ring electrode provided in a ring region, which surrounds the gate runner region in the plan view;
- a termination region surrounding the ring region in the plan view;
- and
- a high-concentration region of the second conductivity type, the high-concentration region having an impurity concentration higher than an impurity concentration of the base layer, and having a pn junction interface at a position deeper than a position of a bottom of the first trench, wherein
- the ring electrode is in contact with the high-concentration region.
Dependencies are inferred from the claim text.