Semiconductor device

A semiconductor device comprising:

• a substrate having a first portion in a cell array region and a second portion in a peripheral circuit region;
• a peripheral circuit structure including a peripheral circuit disposed on the substrate and peripheral circuit wiring connected to the peripheral circuit;
• and
• a cell array structure disposed on the peripheral circuit structure,
• wherein the cell array structure in the cell array region includes
• a plurality of bit lines disposed on the peripheral circuit structure and extending in a first direction,
• a plurality of word lines extending on the plurality of bit lines in a second direction that is different than the first direction,
• an active pattern disposed between a first word line and a second word line of the plurality of word lines,
• a cell landing pad connected to the active pattern, and
• a cell capacitor disposed on the cell landing pad,
• werein the the cell array structure in the peripheral circuit region includes
• a peripheral landing pad including the same material as the cell landing pad and disposed at the same level as the cell landing pad,
• at least one peripheral capacitor disposed at the same level as the cell capacitor and disposed on the peripheral landing pad,
• an upper wiring disposed on the peripheral capacitor,
• an upper conductive contact plug connecting the peripheral capacitor and the upper wiring to each other, and
• a lower conductive contact plug connecting the peripheral landing pad and the peripheral circuit structure to each other, and
• wherein the peripheral capacitor includes
• a peripheral lower electrode connected to the peripheral landing pad,
• a peripheral upper electrode covering the peripheral lower electrode, and
• a peripheral dielectric film disposed between the peripheral lower electrode and the peripheral upper electrode.

A semiconductor device comprising:

• a substrate having a first portion in a cell array region and a second portion in a peripheral circuit region;
• a peripheral circuit structure including a peripheral circuit disposed on the substrate and peripheral circuit wiring connected to the peripheral circuit;
• and
• a cell array structure disposed on the peripheral circuit structure,
• wherein the cell array structure in the cell array region includes
• a plurality of bit lines disposed on the peripheral circuit structure and extending in a first direction,
• a plurality of word lines extending on the plurality of bit lines in a second direction that is different than the first direction,
• an active pattern disposed between a first word line and a second word line of the plurality of word lines,
• a cell landing pad connected to the active pattern, and
• a cell capacitor disposed on the cell landing pad,
• wherein the cell array structure in the peripheral circuit region includes
• a first conductive pad and a second conductive pad each disposed at the same level as an end of the cell capacitor, and
• an upper insulation layer covering the first conductive pad and the second conductive pad, and disposed between the first conductive pad and the second conductive pad,
• each of the first conductive pad and the second conductive pad has a planar line shape on a plane,
• the first conductive pad and the second conductive pad are arranged alternately with each other to at least partially overlap each other, and
• a first peripheral sub-capacitor is configured to the first conductive pad, the second conductive pad, and the upper insulation layer.