Boundary design to reduce memory array edge cmp dishing effect

An integrated chip, comprising:

• a memory region within a substrate;
• a first isolation structure disposed within the substrate adjacent to the memory region, wherein the first isolation structure has a first upper surface region and a second upper surface region laterally adjacent to the first upper surface region, the first upper surface region being vertically above the second upper surface region;
• and
• a gate stack arranged on the first upper surface region.

An integrated chip, comprising:

• a plurality of memory devices disposed within an array in a memory region of a substrate, the plurality of memory devices respectively comprising a select gate and a control gate separated by a charge trapping layer;
• a first isolation structure comprising one or more first dielectric materials disposed within the substrate;
• a second isolation structure comprising a second dielectric material disposed within the substrate, wherein the second isolation structure has a different shape than the first isolation structure and wherein the first isolation structure is between the second isolation structure and the plurality of memory devices;
• a plurality of gate stacks arranged over the second isolation structure;
• a first wall structure arranged over a first surface region of the first isolation structure, wherein the first wall structure comprises a same material as the plurality of memory devices;
• and
• a second wall structure arranged over a second surface region of the first isolation structure, wherein the second surface region is vertically above the first surface region.