Semiconductor device including word line signal path

A semiconductor device comprising:

• a first connection region, a second connection region, and a first memory block region that is between, in a first direction, the first connection region and the second connection region;
• a first peripheral circuit region vertically overlapping with the first memory block region;
• first memory cells in the first memory block region;
• a first word line extending into the first and second connection regions by crossing the first memory block region, and electrically connected to the first memory cells;
• a sub-word line driver in the first peripheral circuit region;
• and
• a first word line signal path electrically connecting the first word line and the sub-word line driver,
• wherein the first word line signal path includes at least one first routing contact coupled to the first word line in the first connection region, and at least one second routing contact coupled to the first word line in the second connection region.

A semiconductor device comprising:

• a first structure including connection regions and memory block regions alternately and repeatedly arranged in a first direction;
• and
• a second structure arranged in the first direction, including peripheral circuit regions, and vertically overlapping with the first structure,
• wherein the connection regions include a first edge connection region, a second edge connection region, and intermediate connection regions between the first edge connection region and the second edge connection region,
• wherein each of the memory block regions is between a pair of adjacent connection regions among the connection regions,
• wherein the first structure includes:
• memory cells in each of the memory block regions;
• and
• word lines electrically connected to the memory cells by crossing the memory block regions and extending into the connection regions,
• wherein the second structure includes sub-word line drivers in each of the peripheral circuit regions,
• wherein the first and second structures further include word line signal paths electrically connecting the word lines and the sub-word line drivers, and
• wherein the word line signal paths include:
• routing interconnection lines crossing the memory block regions and extending into the connection regions;
• routing contacts in each of the connection regions and electrically connecting the word lines and the routing interconnection lines;
• and
• routing structures electrically connecting the routing interconnection lines and the sub-word line drivers.