Memory device

Abstract

A memory device that can be scaled down or highly integrated is provided. The memory device includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode and a second electrode. The second capacitor includes the first electrode and a third electrode. One of a source and a drain of the first transistor is electrically connected to the second electrode. One of a source and a drain of the second transistor is electrically connected to the third electrode. A gate of the third transistor is electrically connected to the second electrode. The first electrode includes a portion overlapping with each of the second electrode, the third electrode, the first transistor, and the second transistor, and is supplied with a fixed potential or a ground potential.

Dependencies are inferred from the claim text.