Semiconductor memory device

A semiconductor memory device comprising:

• a conductive pattern on a substrate;
• a lower electrode which is connected to the conductive pattern, extends in a first direction perpendicular to an upper surface of the substrate, and includes a first portion and a second portion, the first portion of the lower electrode being disposed between the conductive pattern and the second portion of the lower electrode;
• a plurality of electrode side wall supports that support the lower electrode and are in contact with a side wall of the lower electrode;
• a capacitor dielectric film on the lower electrode and each of the plurality of electrode side wall supports;
• and
• an upper electrode on the capacitor dielectric film,
• wherein the first portion of the lower electrode has an increasing width in the first direction away from the conductive pattern, a width of the first portion of the lower electrode being measured in a second direction parallel to the upper surface of the substrate,
• wherein a slope of the side wall of the first portion of the lower electrode is different from a slope of the side wall of the second portion of the lower electrode,
• wherein the plurality of electrode side wall supports include an uppermost electrode side wall support that is farthest away from the conductive pattern in the first direction,
• wherein the uppermost electrode side wall support includes a bottom surface that is adjacent to the conductive pattern and an upper surface opposite to the bottom surface of the uppermost electrode side wall support in the first direction, and
• wherein a part of the first portion of the lower electrode protrudes in the first direction beyond the upper surface of the uppermost electrode side wall support.

A semiconductor memory device comprising:

• a substrate which includes an active region defined by an element separation film and extending in a first direction, the active region including a first portion and a pair of second portions disposed on opposite sides of the first portion and the first direction being parallel to an upper surface of the substrate;
• a word line which extends in a second direction parallel to the upper surface of the substrate and different from the first direction, is buried in the substrate and the element separation film, and is disposed between the first portion of the active region and one of the pair of second portions of the active region;
• a bit line contact connected to the first portion of the active region;
• a bit line which is connected to the bit line contact and extends in a third direction different from the first direction and the second direction and is disposed on the bit line contact;
• a landing pad connected to the second portion of the active region;
• and
• a capacitor connected to the landing pad and disposed on the landing pad,
• wherein the capacitor includes a lower electrode connected to the landing pad and extending in the third direction, a plurality of electrode side wall supports which support the lower electrode and are in contact with a side wall of the lower electrode,
• an electrode capping support which is disposed on the lower electrode and is in contact with an upper face of the lower electrode,
• a capacitor dielectric film on the lower electrode, each of the plurality of electrode side wall supports, and the electrode capping support, and
• an upper electrode on the capacitor dielectric film,
• wherein the lower electrode includes a first portion of the lower electrode and a second portion of the lower electrode,
• wherein the first portion of the lower electrode has an increasing width in the third direction away from the landing pad,
• wherein the electrode capping support is in contact with the second portion of the lower electrode, and
• wherein a slope of the side wall of the first portion of the lower electrode is different from a slope of the side wall of the second portion of the lower electrode.