Second-level metallization testable fully integrated and multi-functional static random access memory and scannable latches

A static random access memory (SRAM) structure, comprising:

• a wafer comprising a first metallization (M1) layer, a second metallization (M2) layer on which the M1 layer is disposed and multiple additional metallization layers on or over which the M2 layer is disposed;
• and
• a fully functional SRAM cell comprising:
• word line and bit line circuitry limited to the M1 layer and the M2 layer;
• and
• power distribution circuitry limited to the M2 layer.

A method of static random access memory (SRAM) structure processing, the method comprising:

• processing a wafer to comprise a first metallization (M1) layer and a second metallization (M2) layer on which the M1 layer is disposed;
• assembling a fully functional SRAM cell comprising word line and bit line circuitry limited to the M1 layer and the M2 layer, power distribution circuitry limited to the M2 layer and SRAM circuitry, a peripheral circuit and a logic circuit limited to the M1 layer and the M2 layer;
• testing the SRAM cell to determine whether a yield of the processing and the assembling exceeds a threshold;
• and
• executing failure analysis of the SRAM cell when the yield does not exceed the threshold and iteratively repeating the processing and the assembling.

A static random access memory (SRAM) structure testing method, comprising:

• forming an initial SRAM cell in first and second metallization (M1 and M2) layers;
• determining, from results of a test of the initial SRAM cell, whether an initial yield exceeds a first threshold;
• executing failure analysis of the initial SRAM cell when the initial yield does not exceed the first threshold and iteratively restarting the method;
• and
• completing formation of a final SRAM cell in the M1 layer and the M2 layer and in additional metallization layers of a wafer when the initial yield exceeds the first threshold.