Semiconductor structure including transistor with different channel lengths and method for manufacturing the same

A method for manufacturing a semiconductor structure, comprising:

• forming a first patterned structure on a memory region of a base structure and forming a second patterned structure and a third patterned structure on a logic region of the base structure, the logic region being displaced from the memory region, each of the first patterned structure, the second patterned structure and the third patterned structure including
• a patterned fin,
• a patterned stack disposed on the patterned fin, the patterned stack including a channel portion and a sacrificial portion disposed beneath the channel portion in a Z direction, the channel portion having two channel ends opposite to each other in an X direction transverse to the Z direction,
• two inner spacers disposed at two opposite sides of the sacrificial portion in the X direction and disposed beneath the two channel ends of the channel portion in the Z direction, and
• a dummy gate portion disposed over the patterned stack and elongated in a Y direction transverse to the X direction and the Z direction, the channel portion having two end surfaces which are opposite to each other in the X direction and which are exposed from the dummy gate portion;
• and
• performing an etching process to selectively recess the two end surfaces of the channel portion in the second patterned structure without recessing the two end surfaces of the channel portion in the third patterned structure.

A semiconductor structure, comprising:

• first transistors disposed on a memory region of a substrate, and a second transistor and a third transistor disposed on a logic region of the substrate, each of the first transistors, the second transistor and the third transistor including
• two source/drain portions spaced apart from each other in an X direction,
• a channel portion extending between the two source/drain portions in the X direction to terminate at two channel ends, and having a width in a Y direction transverse to the X direction,
• a gate electrode elongated in the Y direction, and disposed around the channel portion, and
• two inner spacers disposed beneath the two channel ends of the channel portion so as to separate the gate electrode from the two source/drain portions,
• the width of the channel portion of the second transistor being greater than the width of the channel portion of the third transistor,
• a contact surface between each of the two inner spacers and the channel portion in the second transistor having a dimension in the X direction which is smaller than a dimension in the X direction of a contact surface between each of the two inner spacers and the channel portion in the third transistor.