Digital phase-locked loops

A system comprising:

• a controller;
• a transceiver communicatively coupled to the controller, the transceiver comprising a digital phase-locked loop;
• and
• at least one antenna electrically coupled to the transceiver,
• wherein the digital phase-locked loop comprises:
• a first clock divider to divide a first clock signal comprising a first clock rate to generate a second clock signal comprising a second clock rate less than the first clock rate;
• a decimation filter to convert an input signal at the first clock rate to an output signal at the second clock rate;
• a proportional integral filter to filter the output signal at the second clock rate to generate a filtered output signal;
• a signal conditioner to condition the filtered output signal at the second clock rate to generate a conditioned output signal;
• and
• a digitally controlled oscillator to generate a carrier clock signal in response to the conditioned output signal.

A method comprising:

• dividing a first clock signal comprising a first clock rate to generate a second clock signal comprising a second clock rate less than the first clock rate;
• converting, via a decimation filter, an input signal at the first clock rate to an output signal at the second clock rate;
• filtering, via a proportional integral filter, the output signal at the second clock rate to generate a filtered output signal;
• conditioning the filtered output signal at the second clock rate to generate a conditioned output signal;
• and
• generating, via a digitally controlled oscillator, a carrier clock signal in response to the conditioned output signal.