Dithering based digital to time converter linearization technique
AssigneeUniversity of Southern California
InventorsShuo-Wei Chen, Qiaochu Zhang
Life of this patent
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Abstract
An electrical circuit for clock generation includes a digital-to-time converter error scrambler configured to randomize error in a digital-to-time converter (DTC) and configured to suppress spurs of the electrical circuit, a background error compensator configured to mitigate a timing mismatch between an injection of a reference signal into the DTC at a first point and an injection of the reference signal into the DTC as a second point, and a background delay equalizer configured to calibrate errors of the electrical circuit.
Claims20
An electrical circuit for clock generation comprising:
- a digital-to-time converter error scrambler configured to randomize error in a digital-to-time converter (DTC) and configured to suppress spurs of the electrical circuit;
- a background error compensator configured to mitigate a timing mismatch between an injection of a reference signal into an oscillator at a first point and an injection of the reference signal into the oscillator at a second point;
- and
- a background delay equalizer configured to calibrate errors of the electrical circuit.
An electrical circuit for clock generation comprising:
- an oscillator;
- a digital-to-time converter (DTC) error scrambler configured to randomize error in a DTC and configured to suppress spurs of the electrical circuit, wherein the DTC error scrambler comprises control code to control a delay of one or more injection DTCs;
- a background error compensator configured to mitigate a timing mismatch between an injection of a reference signal into the oscillator at a first point and an injection of the reference signal into the oscillator at a second point;
- and
- a background delay equalizer configured to calibrate errors of the electrical circuit, wherein the errors comprise a plurality of error components.
A method comprising:
- controlling, using a digital-to-time converter (DTC) error scrambler, a delay of one or more injection DTCs of an electrical circuit;
- mitigating, using a background error compensator, a timing mismatch between an injection of a reference signal into an oscillator at a first point and an injection of the reference signal into the oscillator at a second point;
- and
- calibrating, using a delay equalizer, error of the electrical circuit, the error comprising a plurality of error components.
Dependencies are inferred from the claim text.