Apparatus and method for generating clock to increase power efficiency

A method for generating a clock, the method comprising:

• monitoring a first bit error rate of a first signal received based on a first clock signal, the first clock signal having a specified frequency;
• based on the first bit error rate being equal to or greater than a threshold value, connecting a first boosting current source with an oscillator, the first boosting current source being included in a phase locked loop circuit;
• and
• based on the first bit error rate being less than the threshold value, disconnecting a second boosting current source from the oscillator, wherein the second boosting current source is previously connected with the oscillator.

An apparatus for generating a clock, the apparatus comprising:

• a phase locked loop circuit configured to generate, through an inductor-capacitor oscillator, a first clock signal having a specified frequency;
• a monitoring circuit configured to monitor a first bit error rate of a first signal received based on the first clock signal, thereby generating a monitoring result;
• and
• a control logic circuit configured to control the phase locked loop circuit based on the monitoring result,
• wherein the inductor-capacitor oscillator includes:
• an inductor-capacitor tank in which an inductor and a capacitor are connected in parallel, and
• a plurality of cells, each cell of the plurality of cells including a plurality of transistors, the plurality of cells being connected with each other in parallel, and
• wherein the control logic circuit is configured to, based on the first bit error rate being equal to or greater than a threshold value, connect a first cell from the plurality of cells with the inductor-capacitor tank.