Semiconductor system for monitoring results of determination of duty ratio of data clock signals

A semiconductor device comprising:

• a duty ratio determination circuit configured to generate a duty information signal in response to receiving a first data clock signal and a second data clock signal in phase or in reverse phase according to a phase selection signal and determining a duty ratio of the first data clock signal and the second data clock signal during a time period when a duty monitoring enable signal for performing a duty monitoring operation is enabled;
• and
• a data transfer circuit configured to latch the duty information signal when a mode register command is enabled, configured to generate first data or second data from the latched duty information signal based on a phase selection signal, and
• the data transfer circuit configured to output the first data or the second data to a controller.

A method comprising:

• during a first time period, receiving a first data clock signal and a second data clock signal either in phase or in reverse phase;
• during the first time period, determining a duty ratio of the first data clock signal and the second data clock signal;
• generating a duty information signal in response to determining the duty ratio of the first data clock signal and the second data clock signal;
• and
• outputting data generated from the duty information signal.