Logic control circuit, flip-flop and pulse generating circuit

A logic control circuit, comprising:

• a first MOS transistor, a second MOS transistor, a third MOS transistor, and an output circuit;
• a first end of the first MOS transistor is connected to a power supply, and a second end of the first MOS transistor is connected to a first end of the second MOS transistor;
• a second end of the second MOS transistor is connected to a first end of the third MOS transistor, and a second end of the third MOS transistor is grounded;
• the second end of the first MOS transistor is further used to connect to a first end of the output circuit, a second end of the output circuit serves as an output terminal of the logic control circuit, and the second end of the output circuit is further used to connect to a control terminal of the first MOS transistor, so as to control on/off of the first MOS transistor through a pulse signal at the second end of the output circuit;
• a control terminal of the second MOS transistor is used to receive a first clock signal, and a control terminal of the third MOS transistor is used to receive a second clock signal, a waveform of the second clock signal is the same as that of the first clock signal, and the second clock signal is delayed by a preset duration relative to the first clock signal;
• when the first MOS transistor is switched on, the second end of the first MOS transistor is in a high level, and when level of the first clock signal is different from that of the second clock signal, the second MOS transistor or the third MOS transistor is switched off, so as to keep the second end of the first MOS transistor in a high level;
• and
• when the first MOS transistor is switched off, and when the level of the first clock signal is the same as that of the second clock signal, the second MOS transistor and the third MOS transistor are both switched on, so as to set the second end of the first MOS transistor to a low level.