Power management apparatus and method

A system on chip (SoC) comprising at least one of a plurality of SoC power domains and a plurality of SoC clock domains and configured to be coupled to a power management integrated circuit (PMIC);

• wherein each of the SoC and the PMIC comprise a shared key;
• and wherein the SoC is configured to:
• generate a challenge;
• output the challenge to the PMIC;
• generate an expected-challenge-response determined from the challenge and the shared key;
• receive a challenge-response from the PMIC;
• determine whether the challenge-response is valid by comparing the challenge response and the expected-challenge-response;
• and depending on an operating state and in response to the challenge-response being different to the expected-challenge-response:
• (i) apply a reset to the SoC, or
• (ii) output a control signal to the PMIC to supply power to a subset of the plurality of SoC power domains and/or
• (iii) enable the clocks of a subset of the plurality of SoC clock domains.

A method of operating a power management integrated circuit (PMIC) configured to be coupled to a system on chip (SoC) comprising at least one of a plurality of SoC power domains and a plurality of SoC clock domains, wherein each of the PMIC and the SoC comprise a shared key, and wherein the method comprises:

• generating a challenge;
• outputting the challenge to the SoC;
• generating an expected-challenge-response determined from the challenge and the shared key;
• receiving a challenge-response from the SoC;
• comparing the challenge response and the expected-challenge-response;
• and depending on an operating state and in response to the challenge-response being different to the expected-challenge-response:
• (i) applying a reset to the SoC, or
• (ii) supplying power to a subset of the plurality of SoC power domains and/or
• (iii) enabling clocks of a subset of the plurality of SoC clock domains.