Utilizing memory chip through-silicon vias for connecting logic chip to substrate

Abstract

An integrated circuit device with a chip stacking architecture that is effective in cooling a higher-power logic chip as well as effective in providing power and signal connections and high bandwidth to the logic chip. The integrated circuit device includes a chip stacking architecture that includes a substrate, one or more memory chips stacked on top of the substrate and a logic chip stacked on top of the one or more memory chips, where the logic chip communicates with the substrate via through-silicon vias located in the memory chip(s). A portion of the through-silicon vias in the memory chip(s) are electronically disconnected from a specific memory chip and therefore are able to be used to enable the logic chip to communicate with the substrate.

Dependencies are inferred from the claim text.