Semiconductor package

A semiconductor package, comprising:

• a package substrate including first bonding pads and second bonding pads that are alternately arranged in a single row along a first direction, third bonding pads that are spaced apart from the first bonding pads in a second direction intersecting the first direction, fourth bonding pads that are spaced apart from the second bonding pads in the second direction, fifth bonding pads and sixth bonding pads that are alternately arranged in a single row along the first direction, seventh bonding pads that are spaced apart from the fifth bonding pads in the second direction, and eighth bonding pads that are spaced apart from the sixth bonding pads in the second direction;
• a first chip stack including first chips that are stacked on the package substrate, each first chip including first signal pads and first power/ground pads that are alternately arranged in a single row along a first direction;
• a second chip stack including second chips that are stacked on the first chip stack, each second chip including second signal pads and second power/ground pads that are alternately arranged in a single row along the first direction;
• a third chip stack including third chips that are stacked on the package substrate, each third chip including third signal pads and third power/ground pads that are alternately arranged in a single row along the first direction;
• a fourth chip stack including fourth chips that are stacked on the third chip stack, each fourth chip including fourth signal pads and fourth power/ground pads that are alternately arranged in a single row along the first direction;
• first upper wires that connect the second signal pads of one of the second chips to the third bonding pads;
• second upper wires that connect the second power/ground pads of the one of the second chips to the fourth bonding pads;
• third upper wires that connect the fourth signal pads of one of the fourth chips to the seventh bonding pads;
• and
• fourth upper wires that connect the fourth power/ground pads of one of the fourth chips to the eighth bonding pads.

A semiconductor package, comprising:

• a package substrate;
• a first chip stack including first chips that are stacked on the package substrate, each first chip including first signal pads and first power/ground pads that are alternately arranged in a single row along a first direction;
• a second chip stack including second chips that are stacked on the first chip stack, each second chip including second signal pads and second power/ground pads that are alternately arranged in a single row along the first direction;
• a third chip stack including third chips that are stacked on the package substrate, each third chip including third signal pads and third power/ground pads that are alternately arranged in a single row along the first direction;
• a fourth chip stack including fourth chips that are stacked on the third chip stack, each fourth chip including fourth signal pads and fourth power/ground pads that are alternately arranged in a single row along the first direction;
• lower wires connecting the first chip stack to the package substrate and connecting the third chip stack to the package substrate;
• upper wires connecting the second chip stack to the package substrate and connecting the fourth chip stack to the package substrate;
• first connection wires that connect the first power/ground pads of a first one of the first chips and the second power/ground pads of a first one of the second chips;
• and
• second connection wires that connect the third power/ground pads of a first one of the third chips and the fourth power/ground pads of a first one of the fourth chips,
• wherein the first one of the first chips is adjacent to the first one of the second chips, and
• wherein the first one of the third chips is adjacent to the first one of the fourth chips.

A semiconductor package, comprising:

• a package substrate including first bonding pads and second bonding pads that are alternately arranged in a single row along a first direction, third bonding pads that are spaced apart from the first bonding pads in a second direction intersecting the first direction, fourth bonding pads that are spaced apart from the second bonding pads in the second direction, fifth bonding pads and sixth bonding pads that are alternately arranged in a single row along the first direction, seventh bonding pads that are spaced apart from the fifth bonding pads in the second direction, and eighth bonding pads that are spaced apart from the sixth bonding pads in the second direction;
• a first chip stack including first chips that are stacked on the package substrate, each first chip including first signal pads and first power/ground pads that are alternately arranged in a single row along a first direction;
• a second chip stack including second chips that are stacked on the first chip stack, each second chip including second signal pads and second power/ground pads that are alternately arranged in a single row along the first direction;
• a third chip stack including third chips that are stacked on the package substrate, each third chip including third signal pads and third power/ground pads that are alternately arranged in a single row along the first direction;
• a fourth chip stack including fourth chips that are stacked on the third chip stack, each fourth chip including fourth signal pads and fourth power/ground pads that are alternately arranged in a single row along the first direction;
• a controller chip disposed between the first chip stack and the third chip stack on the package substrate, the controller chip including first and second chip pads that are alternately arranged along the first direction and third and fourth chip pads that are alternately arranged along the first direction and that are spaced apart from the first and second chip pads in the second direction;
• first upper wires that connect the second signal pads of one of the second chips to the first chip pads;
• second upper wires that connect the second power/ground pads of the one of the second chips to the second chip pads;
• third upper wires that connect the fourth signal pads of one of the fourth chips to the third chip pads;
• and
• fourth upper wires that connect the fourth power/ground pads of one of the fourth chips to the fourth chip pads.