Semiconductor package and method of implementing redistribution layer in ball grid array

A semiconductor package comprising:

• a first semiconductor device;
• a plurality of second semiconductor devices, wherein the first semiconductor device is configured to control the plurality of second semiconductor devices;
• and
• a connection substrate on which the first semiconductor device and the plurality of second semiconductor devices are provided,
• wherein each of the plurality of second semiconductor devices comprises:
• a plurality of first semiconductor chips sequentially stacked in a vertical direction, at least one of the plurality of first semiconductor chips comprising a plurality of first through electrodes connecting the plurality of first semiconductor chips to each other, each of the plurality of first semiconductor chips having a first width in a horizontal direction;
• a second semiconductor chip under the plurality of first semiconductor chips, the second semiconductor chips comprising a plurality of second through electrodes connecting the second semiconductor chip to the plurality of first semiconductor chips, the second semiconductor chip having a second width in the horizontal direction that is greater than the first width;
• a redistribution layer under the second semiconductor chip, the redistribution layer having a third width in the horizontal direction that is substantially equal to the second width;
• a plurality of first connection bumps between the second semiconductor chip and the redistribution layer, and connecting the second semiconductor chip with the redistribution layer, each of the plurality of first connection bumps having a first size;
• and
• a plurality of second connection bumps under the redistribution layer, and connecting the redistribution layer with an external device, each of the plurality of second connection bumps having a second size that is greater than the first size.

A semiconductor package comprising:

• a first dynamic random access memory (DRAM) chip having a first width in a horizontal direction;
• a plurality of second DRAM chips sequentially stacked in a vertical direction under the first DRAM chip, at least one of the plurality of second DRAM chips comprising a plurality of first through electrodes connecting the plurality of first semiconductor chips to each other and to the first DRAM chip, each of the plurality of second DRAM chips having a second width in the horizontal direction that is substantially equal to the first width;
• a buffer chip under the plurality of second DRAM chips, the buffer chip comprising a plurality of second through electrodes connecting to the first DRAM chip and the plurality of second DRAM chips, the buffer chip having a third width in the horizontal direction that is greater than the first width;
• a redistribution layer under the buffer chip, the redistribution layer having a fourth width in the horizontal direction that is substantially equal to the third width;
• a plurality of first connection bumps between the buffer chip and the redistribution layer, and connected to the plurality of second through electrodes and the redistribution layer, each of the plurality of first connection bumps having a first size;
• a plurality of second connection bumps under the redistribution layer, and connected to the redistribution layer, each of the plurality of second connection bumps having a second size that is greater than the first size;
• and
• an encapsulant encapsulating the first DRAM chip, the plurality of second DRAM chips and the buffer chip, the encapsulant covering side surfaces of the first DRAM chip, side surfaces of the plurality of second DRAM chips, and at least a portion of an upper surface of the buffer chip,
• wherein a number of the plurality of second connection bumps is less than a number of the plurality of first connection bumps,
• wherein a first number of first connection bumps among the plurality of first connection bumps are respectively connected to a second number of second connection bumps among the plurality of second connection bumps via the redistribution layer,
• wherein the first DRAM chip, the plurality of second DRAM chips and the buffer chip are electrically connected to an external device by the first number of first connection bumps, the redistribution layer and the second number of second connection bumps, and
• wherein a second number of first connection bumps among the plurality of first connection bumps are floated without connections with the redistribution layer, the plurality of second connection bumps and the external device.