Microelectronic device obtained by 3d integration and corresponding production method

A three-dimensional, or 3D, microelectronic structure for an integrated semiconductor product, said 3D microelectronic structure comprising a first microelectronic device produced on a top wafer, and a second microelectronic device produced on a bottom wafer on which the top wafer is bonded by hybrid bonding after being turned over vertically, wherein the bottom wafer and the top wafer each comprise a substantially flat substrate and an interconnect structure formed on top of said substrate, wherein:

• the respective interconnect structure of each of the top and bottom wafers is a vertical stack of at least two interconnect levels directly superimposed and each comprising a hybrid layer essentially composed of a dielectric material, namely, respectively:
• an upper interconnect level (HBM), with metal bonding pads formed in the dielectric material and adapted to interact with corresponding metal bonding pads in the other wafer for hybrid bonding of the top wafer to the bottom wafer;
• and,
• a horizontal interconnect level (MX) which is directly below the upper interconnect level (HBM), with horizontal metallization elements,
• the respective metal bonding pads of each of the top and bottom wafers are distributed substantially homogeneously on the top surface of the upper interconnect level (HBM) of the interconnect structure of said wafer, with a bonding pitch, defined as the maximum spacing between adjacent bonding pads horizontally in the plane of said top surface, which is below a predetermined associated threshold;
• the respective metal bonding pads of each of the top and bottom wafers comprise bonding pads of a first type, which are electrically insulated from any horizontal metallization element in the horizontal interconnect level (MX) of the interconnect structure of said wafer;
• and,
• the respective metal bonding pads of each of the top and bottom wafers further comprise bonding pads of a second type, which are each electrically coupled to at least one underlying horizontal metallization element formed in the horizontal interconnect level (MX) of the interconnect structure of said wafer.