Semiconductor packages

A semiconductor package, comprising:

• a lower redistribution layer comprising lower redistribution patterns stacked in a vertical direction;
• a first semiconductor chip on the lower redistribution layer;
• a mold layer on the lower redistribution layer and covering the first semiconductor chip;
• an upper redistribution layer on the mold layer;
• and
• connection terminals on the upper redistribution layer,
• wherein the upper redistribution layer comprises:
• a first upper insulating pattern on a top surface of the mold layer;
• a second upper insulating pattern in contact with the first upper insulating pattern;
• upper redistribution patterns between the first upper insulating pattern and the second upper insulating pattern;
• and
• under-bump patterns that penetrate the second upper insulating pattern and connect to the upper redistribution patterns, and
• wherein at least one of the under-bump patterns is connected to at least two of the connection terminals.

A semiconductor package, comprising:

• a lower redistribution layer comprising lower redistribution patterns that are vertically stacked in a vertical direction;
• a first semiconductor chip on the lower redistribution layer;
• a connection structure on the lower redistribution layer and horizontally spaced apart from the first semiconductor chip;
• an upper redistribution layer on the first semiconductor chip and the connection structure, the upper redistribution layer comprising under-bump patterns;
• a second semiconductor chip on the upper redistribution layer;
• and
• connection terminals between the upper redistribution layer and the second semiconductor chip,
• wherein the connection terminals are two-dimensionally arranged, when viewed in a plan view,
• wherein the under-bump patterns comprise:
• a first under-bump pattern connected to at least two of the connection terminals, the first under-bump pattern comprising pad portions and an interconnection portion between the pad portions;
• and
• a second under-bump pattern connected to one of the connection terminals,
• wherein the upper redistribution layer comprises upper redistribution patterns, that are connected to the under-bump patterns, and an upper insulating pattern, that is on the upper redistribution patterns, and
• wherein the interconnection portion of the first under-bump pattern is on the upper insulating pattern.