Semiconductor package

A semiconductor package comprising:

• a wiring board;
• a semiconductor chip on a top surface of the wiring board and electrically connected to the wiring board;
• a molding layer between the wiring board and the semiconductor chip and molding the wiring board and the semiconductor chip;
• and
• solder resist patterns surrounded by the molding layer under the semiconductor chip, wherein the solder resist patterns are arranged under one side of the semiconductor chip.

A semiconductor package comprising:

• a wiring board including a wiring pattern;
• a solder resist layer on a top surface of the wiring board, the solder resist layer defining an opening that exposes the wiring pattern;
• a semiconductor chip electrically connected to the wiring pattern of the wiring board and mounted on the wiring board;
• a molding layer in the opening between the wiring board and the semiconductor chip and molding the wiring board and the semiconductor chip;
• solder resist patterns arranged in the opening between the wiring board and the semiconductor chip and surrounded by the molding layer;
• and
• a plurality of signal bumps surrounded by the molding layer between the wiring board and the semiconductor chip, the plurality of signal bumps electrically connecting the wiring board and the semiconductor chip, wherein the plurality of signal bumps are arranged in a line under a center of the semiconductor chip along a first horizontal direction, and
• wherein the solder resist patterns are arranged in a line along the first horizontal direction under a first edge of the semiconductor chip extending in the first horizontal direction.