Semiconductor device and method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, comprising:

• forming, on a first surface of a substrate, a channel layer and source/drain patterns disposed in a first direction parallel to the first surface of the substrate interposing the channel layer;
• forming a gate structure extending in a second direction crossing the first direction and at least partially surrounding the channel layer in the second direction;
• forming a gate separation pattern crossing the gate structure and at least partially penetrating the gate structure in a third direction perpendicular to the first direction and the second direction;
• forming a through electrode at least partially penetrating the gate separation pattern in the third direction;
• and
• forming an air gap between the gate structure and a first sidewall and a second sidewall of the through electrode within the gate separation pattern.

A semiconductor device, comprising:

• a base insulation layer comprising a first surface and a second surface facing the first surface;
• a channel layer on the first surface of the base insulation layer;
• source/drain patterns disposed in a first direction parallel to the first surface of the base insulation layer interposing the channel layer;
• a gate structure extending in a second direction crossing the first direction on the first surface of the base insulation layer and at least partially surrounding the channel layer;
• a gate separation pattern crossing the gate structure and at least partially penetrating the gate structure in a third direction perpendicular to the first direction and the second direction;
• an interlayer insulation layer at least partially covering the source/drain patterns, the gate structure and the gate separation pattern;
• an upper wire structure on the interlayer insulation layer;
• a lower wire structure on the second surface of the base insulation layer;
• a power rail on the lower wire structure and at least partially penetrating the base insulation layer in the third direction;
• and
• a through electrode at least partially penetrating the gate separation pattern in the third direction and comprising a first end coupled to the power rail,
• wherein the gate separation pattern comprises an air gap.