Semiconductor package including a solder ball

A semiconductor package, comprising:

• a package body having a fan-in area and a fan-out area at least partially surrounding the fan-in area, wherein a body wiring structure is formed in the fan-out area of the package body;
• a semiconductor chip disposed in the fan-in area;
• a first redistribution structure disposed on a lower surface of the package body and a lower surface of the semiconductor chip, and comprising a first redistribution element in each of the fan-in area and the fan-out area;
• a first redistribution pad disposed on a lower surface of the first redistribution structure and electrically connected to the first redistribution element;
• a ball land layer disposed on a lower surface of the first redistribution pad;
• a first pad insulating layer disposed on the lower surface of the first redistribution structure and insulating the first redistribution pad and the ball land layer;
• an alignment mark structure disposed in the fan-out area and spaced apart from the first redistribution pad, and disposed inside or on a lower surface of the first pad insulating layer;
• and
• a first solder ball disposed on the lower surface of the first redistribution pad and a lower surface of the ball land layer.

A semiconductor package, comprising:

• a lower package;
• and
• an upper package stacked on the lower package,
• wherein the lower package comprises:
• a package body having a fan-in area and a fan-out area at least partially surrounding the fan-in area, wherein a body wiring structure is formed in the fan-out area of the package body;
• a lower semiconductor chip disposed in the fan-in area;
• a first redistribution structure disposed on a lower surface of the package body and a lower surface of a lower semiconductor chip, and comprising a first redistribution element in each of the fan-in area and the fan-out area;
• a first redistribution pad disposed on a lower surface of the first redistribution structure and electrically connected to the first redistribution element;
• a ball land layer disposed on a lower surface of the first redistribution pad;
• a first pad insulating layer disposed on the lower surface of the first redistribution structure and insulating the first redistribution pad and the ball land layer;
• an alignment mark structure disposed in the fan-out area and spaced apart from the first redistribution pad, and disposed inside or on a lower surface of the first pad insulating layer;
• a first solder ball disposed on a lower surface of each of the first redistribution pad and the ball land layer;
• a second redistribution structure disposed on an upper surface of the package body and an upper surface of the lower semiconductor chip, and comprising a second redistribution element in each of the fan-in area and the fan-out area;
• and
• a second redistribution pad electrically connected to the second redistribution element, wherein the upper package comprises:
• a second solder ball disposed on the second redistribution pad;
• and
• an upper semiconductor chip mounted on the second redistribution structure and electrically connected through the second solder ball.