Semiconductor device and electronic system including the same

A semiconductor device, comprising:

• a semiconductor substrate;
• a peripheral circuit structure including a plurality of peripheral circuits on the semiconductor substrate and a plurality of first bonding pads connected to the peripheral circuits;
• and
• a cell array structure including a plurality of second bonding pads bonded to the first bonding pads, wherein
• the cell array structure includes
• a plurality of separation structures extending in a first direction,
• a stack structure between the plurality of separation structures, the stack structure including a plurality of interlayer dielectric layers and a plurality of conductive patterns that are vertically alternately stacked,
• a source conductive pattern on the stack structure,
• a plurality of vertical channel patterns penetrating the stack structure and connecting to the source conductive pattern;
• a plurality of bit lines extending in a second direction while crossing the stack structure and connecting to the vertical channel patterns, the second direction intersecting the first direction,
• an upper dielectric layer covering the source conductive pattern,
• an upper via penetrating the upper dielectric layer and connecting to the source conductive pattern, and
• a wiring pattern on the upper dielectric layer and connecting to the upper via
• each of the plurality of separation structures includes a dielectric pattern, a stop pattern on the dielectric pattern and adjacent to the source conductive pattern, and a spacer,
• the spacer surrounds the dielectric pattern and at least a portion of the stop pattern, and
• a vertical length of the stop pattern is less than a vertical length of the dielectric pattern.

An electronic system, comprising:

• a semiconductor device including a peripheral circuit structure and a cell array structure on the peripheral circuit structure;
• and
• a controller electrically connected through an input/output pad to the semiconductor device, the controller being configured to control the semiconductor device, wherein
• the peripheral circuit structure includes a plurality of peripheral circuits integrated on a semiconductor substrate and a plurality of first bonding pads connected to the peripheral circuits,
• the cell array structure includes a plurality of second bonding pads bonded to the first bonding pads,
• the cell array structure includes a stack structure, a separation structure penetrating the stack structure, a plurality of vertical channel patterns penetrating the stack structure, a source conductive pattern connected to the vertical channel patterns on the stack structure, an upper dielectric layer covering the source conductive pattern, and an upper via that penetrates the upper dielectric layer,
• the stack structure includes a plurality of interlayer dielectric layers and a plurality of conductive patterns that are vertically alternately stacked,
• the separation structure includes a dielectric pattern and a stop pattern on the dielectric pattern,
• the source conductive pattern is in contact with a top surface of the stop pattern, and
• the upper via connects to the source conductive pattern on the stop pattern.