Memory device and method of manufacturing memory device

A memory device comprising:

• a lower interconnection structure on a substrate, the lower interconnection structure including a plurality of circuit components and a plurality of lower conductive patterns;
• a cell stack structure on the lower interconnection structure, the cell stack structure including a plurality of gate electrodes stacked spaced apart from each other in a vertical direction, the vertical direction perpendicular to an upper surface of the substrate;
• an interlayer insulating layer covering the cell stack structure;
• an upper interconnection structure on the interlayer insulating layer, the upper interconnection structure including a plurality of upper conductive patterns and an external pad;
• an effective contact structure passing through the interlayer insulating layer, the effective contact structure having an upper surface and a lower surface, the upper surface of the effective contact structure being in contact with a first upper pad electrically connected to the external pad, and the lower surface of the effective contact structure being in contact with a first lower pad electrically connected to the circuit components;
• and
• one or more preliminary contact structures respectively passing through the interlayer insulating layer, the one or more preliminary contact structures respectively having a structure same as the effective contact structure,
• wherein the one or more preliminary contact structures are electrically floating.

A memory device comprising:

• a lower chip including a first substrate, a plurality of circuit components on the first substrate, and a lower interconnection structure electrically connected to the plurality of circuit components;
• and
• an upper chip on the lower chip, the upper chip including a second substrate, an upper interconnection structure on an upper surface of the second substrate, an external pad connected to the upper interconnection structure, a cell stack structure including a plurality of gate electrodes stacked and spaced apart from each other in a first direction, the first direction perpendicular to a lower surface of the second substrate, an interlayer insulating layer surrounding a lower surface and a side surface of the cell stack structure, an intermediate interconnection structure below the interlayer insulating layer and bonded to the lower interconnection structure, one or more effective contact structures respectively passing through the interlayer insulating layer, and one or more preliminary contact structures respectively passing through the interlayer insulating layer, the one or more effective contact structures respectively having an upper surface and a lower surface, the upper surface of an effective contact structure being in contact with a first upper pad electrically connected to the external pad, the lower surface of the effective contact structure being in contact with a first lower pad electrically connected to the circuit components, the one or more preliminary contact structures respectively having an upper surface and a lower surface, the upper surface of a preliminary contact structure being in contact with a second upper pad, and the lower surface of the preliminary contact structure being in contact with a second lower pad,
• wherein the one or more preliminary contact structures are electrically floating.