Semiconductor package

A semiconductor package, comprising:

• a lower interconnect structure comprising a plurality of lower dielectric layers and a plurality of lower metal vias formed in the plurality of lower dielectric layers, wherein the plurality of lower metal vias comprise a plurality of lower stacked vias located in different layers of the plurality of lower dielectric layers;
• an upper interconnect structure formed over the lower interconnect structure, wherein the upper interconnect structure comprises a plurality of upper dielectric layers and a plurality of upper metal vias formed in the plurality of upper dielectric layers, and a material of the plurality of upper dielectric layers is different from a material of the plurality of lower dielectric layers;
• a first conductive pad formed over the upper interconnect structure and electrically connected to the plurality of upper metal vias;
• and
• a pillar bump structure comprising a first protrusion and a second protrusion laterally spaced apart from the first protrusion, wherein the first protrusion is in direct contact with a top surface of the first conductive pad.

A semiconductor package, comprising:

• an interconnect structure comprising a plurality of dielectric layers and a plurality of metal lines and a plurality of stacked vias formed in the plurality of dielectric layers,
• a first passivation layer formed over the interconnect structure;
• a second passivation layer formed over the first passivation layer;
• a polymeric layer formed over the second passivation layer;
• and
• a pillar bump structure formed over the polymeric layer, wherein the pillar bump structure comprises a first protrusion extending into the polymeric layer, and a projection area of the first protrusion of the pillar bump structure is spaced apart from projection areas of the plurality of stacked vias.